1. Field of the Invention
The present invention relates to On Die Termination (ODT) in high speed memory modules, and in particular, to select different termination values on each memory chip in systems utilizing memory modules.
2. Description of the Prior Art
In a typical memory system, various memory locations, routing limitations, and signal paths of busses coupled to the individual memories cause timing skew and other signal quality issues. Some compensation may be needed by performing line termination.
FIG. 1 shows a typical fixed passive termination configuration 100 for a data bus according to the related art. The data bus can be modeled as a plurality of transmission line segments 120 as illustrated in FIG. 1. A memory controller 110 controls a plurality of memory devices 130 located along the data bus, and a passive termination resistor 140 is positioned at the end of a final transmission line segment 120 on the data bus to prevent signal reflections caused by standing waves or other phenomenon. Of note is that the passive termination resistor 140 is enabled at all times resulting in an inefficient use of power. Also, the passive termination resistor 140 cannot properly terminate the data bus in all conditions and signal quality of the lines on the data bus is therefore not optimal.
In an attempt to overcome the problems associated with the use of fixed passive terminations such as illustrated in FIG. 1, mode-selected On Die Termination (ODT) has been demonstrated in the related art. However, mode-selected ODT allows only a single termination value to be selected across all the devices on the data bus, which greatly limits the effectiveness. The reason effectiveness is limited is that each device is at a different physical position so signal lines routed on the circuit board will undergo different clock skews.